Specification

 

ADC

2 ADCs - Low power, 10bit, 3 GSPS each ADC (single channel up to 3 GSPS or dual 1.5 GSPS for two independent I and Q channels).
9/9.1 ENOB.
70/68 dBc SFDR.
57/56.8 dB SNR.

DAC

2 DACs - Low noise, 14bit, 2.5 GSPS.
Low noise and inter-modulation distortion (IMD) performance enable high quality synthesis of wideband signal up to 1GHz.

FPGA

StratixIV GX 40nm process TSMC technology, allows real time DSP and data acquisition smooth operation with PCI-EX and other communication interfaces.
Up to 512,200 LEs, 27,376 Kbits RAM, 1288 DSP 18x18 multipliers.

Mechanical specification

6U form factor: 9.2 inches X 6.3 inches (233mm X 160mm).
Single slot, front panel width 0.8 inch (20.3mm).
P1,P2 connectors:VME 160-way.
Utilize VXS 105-way connector P0.

Applications

Platforms:

LAU-S4
Electronic Warfare (e.g. Radar)
WiMAX and LTE front end
Satellite Set-top boxes
WCDMA

LAB-S4
Direct RF Down Conversion.
Medical Imaging
WLAN

LDD-S4
Digital Oscilloscopes
Instrumentation, automatic test equipment

LAD-S4
Data Acquisition Systems
Wideband Communications
Broadband communication systems

 

LAGGER-S4 Ultra Hiigh speed data acquisition board

lagger

Product Overview

David Korman technologies Lagger-S4 is 6U VME and ANSI/VITA 41 (VXS) compliant data acquisition board that combines high density FPGA processing with two 10-bit ADC devices, up to 6 GSPS. The board also contains two 14-bit DAC devices, 2.5 GSPS each with synchronizing mechanism between the DACs (DACs fixed phase alignment, I and Q channels synchronization). Lagger-S4 enables multi-channel signal acquisition.


HSRTSP (High Speed Real Time Signal Processing) board has both analog to digital and digital to analog dual converters, FPGA device for real time DSP processing and all common types of data communication.

VXS Backplane High Speed Serial I/O.

The Lagger-S4 can be used as a VITA 41.4 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.4 MultiGig RT2 P0 connector. Custom or standard communication protocol PCI Express can be run over these links by providing appropriate firmware in the FPGA.

Trigger

A trigger input is provided on the front panel which allows the hardware to be employed in variety of radar and electronic warfare scenarios. One trigger serves all ADC channels, and is sampled using the same sampling clock as both ADCs, up to 6 GSPS.

 

The trigger input may be used to synchronize the data streams from both ADCs on single board, and to synchronize multiple Lagger-S4 boards to within a single sample period.

Power

Single voltage input.

Memory

The Lagger-S4 has up to 24Mb internal memory.

System Monitoring

The Lagger-S4 includes facilities to monitor current and temperature at various points on the board. Current monitoring is implemented for all main power rails.

External Memory

Up to 4Gb DDR3 SDRAM (2 banks, up to 2Gb each).

Ethernet and control interface

Optional 1Gb Ethernet Interface via RJ45 connector on the front panel.
100 Mbps Ethernet interface via RJ45 connector on the front panel.

2 UART's with front and back panel connections,

FPGA

StratixIV GX 40nm process TSMC technology, allows real time DSP and data acquisition smooth operation with PCI-EX and other communication interfaces.


ADC

2 ADCs - Low power, 10bit, 3 GSPS.
Excellent accuracy and dynamic performance.
AutoSync feature for multi-chip systems.

DAC

2 DACs - Low noise, 14bit, 2.5 GSPS.
DACs fixed phase alignment, I and Q channels synchronization.
Low noise and inter-modulation distortion (IMD) performance enable high quality synthesis of wideband signal up to 1GHz.